In some memory systems, memory devices of a memory module are accessed by a memory controller using address and control lines, which are routed such that the address and control signals arrive at each of the memory devices in sequence (e.g., in a flyby topology). With different memory module rank configurations, there may be respective different control/address bus capacitive loading presented by the memory devices. For example, there may be separate control bus lines for each rank while the number of address bus lines is independent of the ranks in the memory system. Because of different loading (or lengths) of signal lines, signals propagating on those signal lines are skewed relative to one-another. The capacitance loading of command/address signal lines may vary depending on the number of memory ranks in the memory subsystem. In a system having more than one rank, the capacitance loading of the address lines may be different from the loading of the control signal lines, resulting in skew between the relative arrival times of control signals and command/address signals. Assuming that the trace impedance in the device loading area and the device pitch are the same for both address and control bus lines, systematic skew is accumulated along the bus between the control pins and the address pins as the control/address signals propagate on the fly-by bus from the first memory device to the last memory device.